Computer Architecture

BSc - Spring Semester
2419, Lectures and exercises, 5.0 ECTS

Lecturer Prof. Dr. Paolo Favaro
Teaching assistants Mr. Adrian Wälchli
Mr. Xiaochen Wang
Mr. Abdelhak Lemkhenter
Location Hörsaal B006 ExWi Building Sidlerstrasse 5
Time Tuesdays 13:15 - 15:15 (lecture) and 15:15 to 16:00 (tutorials)
Exam June 5 2020 from 16.00-18.00 at ExWi, A6

Course description

This course covers fundamental topics in computer architecture. The course will provide an introduction to C programming, MIPS basic architecture and instruction set, pipeline, I/O system, cache and memory. Related issues such as performance and data/control Hazards will also be covered. The students will also get familiar with Assembler programming via practical laboratory sessions with the Raspberry Pi programmable boards.


The following books/sources are recommended:

  1. D. Patterson and J. Hennessy, "Computer Architecture: A Quantitative Approach", Fourth Edition
  2. Reading material on ILIAS.


The exercises and laboratory assignments are a prerequisite for registering for the exam. Guidelines will be specified by the teaching assistants and are available in the SERIE 0 document in ILIAS. All homework assignments and repetition exercise sessions will be necessary for the exam preparation.

Schedule and material

The following table provides an overview of the content of the lectures during the semester. Please check it periodically as it might be updated.

Week Lecture Reading
1 C Introduction ILIAS
3 MIPS Instruction Set Architecture "Patterson&Hennessy", Chapt. 2
4 MIPS Instruction Set Architecture "Patterson&Hennessy", Chapt. 2
5 Performance "Patterson&Hennessy", Chapt. 3,4
6 MIPS Basic Architecture "Patterson&Hennessy", Chapt. 3,4
7 MIPS Basic Architecture "Patterson&Hennessy", Chapt. 3,4
8 Pipeline "Patterson&Hennessy", Chapt. 4
9 Data Hazards "Patterson&Hennessy", Chapt. 4
10 Control Hazards "Patterson&Hennessy", Chapt. 4
11 Multiple Issue Introduction "Patterson&Hennessy", Chapt. 4
12 Memory and Cache Introduction "Patterson&Hennessy", Chapt. 5
13 Cache Performance, IO Systems "Patterson&Hennessy", Chapt. 6
14 Revision ILIAS